Research

Memory Systems

Modern multi-core processors are placing severe pressure on DRAM main memory systems. Several opportunities for innovation exist: exploiting 3D chip stacks, exploiting photonic interconnects, better scheduling policies within multiple memory controllers, increasing the utilization of DRAM row buffers, reducing energy dissipated per DRAM access, QoS guarantees within the memory system, etc.

Hardware Ray Tracing

Hardware Ray Tracing research page.

Design of Large Caches

More than half the area of future chips will be occupied by large cache hierarchies. Large caches will be partitioned into numerous banks connected by an on-chip network -- a non-uniform cache architecture (NUCA). We have looked at designing tools to estimate an optimal cache organization and also explored mechanisms (reconfiguration, data mapping, on-chip network design) to improve a core's access to its data.

 
 

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