Publications

Most publications are copyrighted by IEEE or ACM. Please respect these copyrights. Typically, personal or classroom use is granted; papers cannot be duplicated for commercial purposes. In recent years, the research group has been funded by NSF grant CCF-0430063, NSF CAREER award CCF-0545959, NSF grant CCF-0811249, NSF grant CCF-0916436, SRC Contract 2008-TJ-1847, Intel, HP Labs, and the University of Utah. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation or any other sponsor. Some of our simulation results are derived with Simics that is supported by Wind River .

Books and Book Chapters

• Innovations in the Memory System , Rajeev Balasubramonian, Synthesis Lectures on Computer Architecture , Morgan and Claypool Publishers, 2019.
• Emerging Hardware Technologies for AI & IoT, M. Bojnordi and P. Behnam, Book Chapter of Intelligent Internet of Things, From Device to Fog and Cloud, F. Firouzi, K. Chakrabarty, and S. Nassif(editors), Springer, 2019.
• Multi-Core Cache Hierarchies , Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Synthesis Lectures in Computer Architecture , Morgan and Claypool Publishers, 2011.
• Buses and Crossbars , Rajeev Balasubramonian, Timothy Pinkston, Encyclopedia of Parallel Computing , D. Padua, editor. Springer Science+Business Media, 2011.
• Digital VLSI Chip Design with Cadence and Synopsys CAD Tools , Erik Brunvand, Addison Wesley, 2009. Publisher's site for this book

Conferences, Journals, Workshops, Posters and Technical Reports

2022

• XCRYPT: Accelerating Lattice Based Cryptography with Memristor Crossbar Arrays Sarabjeet Singh, Xiong Fan, Ananth Krishna Prasad, Lin Jia, Anirban Nag, Rajeev Balasubramonian, Mahdi Nazm Bojnordi, Elaine Shi, IEEE MICRO 2022.
• CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe, 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA-2022) Worldwide event, April 2022.

2021

• A Multiply-and-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow Edouard Giacomin, Sumanth Gudaparthi, Juergen Boemmels, Rajeev Balasubramonian, Francky Catthoor, Pierre-Emmanuel Gaillardon, IEEE Transactions on Nanotechnology December 2021.
• OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations Anirban Nag, Rajeev Balasubramonian, 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-54) Worldwide Event, October 2021.
• Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication Adarsh Patil, Vijay Nagarajan, Rajeev Balasubramonian, Nicolai Oswald, 48th Annual International Symposium on Computer Architecture (ISCA-2021) Worldwide Event, June 2021.
• Efficient Oblivious Query Processing for Range and kNN Queries Zhao Chang, Dong Xie, Feifei Li, Jeff M Phillips, Rajeev Balasubramonian, IEEE Transactions on Knowledge and Data Engineering February 2021.

2020

• SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon, 47th International Symposium on Computer Architecture (ISCA-2020) Worldwide Event, June 2020.
• Compact Leakage-Free Support for Integrity and Reliability Meysam Taassori, Rajeev Balasubramonian, Siddhartha Chhabra, Alaa R. Alameldeen, Manjula Peddireddy, Rajat Agarwal, Ryan Stutsman, 47th International Symposium on Computer Architecture (ISCA-2020) Worldwide Event, June 2020.

2019

• Wire-Aware Architecture and Dataflow for CNN Accelerators, Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon, 52nd International Symposium on Microarchitecture (MICRO-52) , Columbus OH, October 2019.
• GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment, Anirban Nag, C.N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon, 52nd International Symposium on Microarchitecture (MICRO-52) , Columbus OH, October 2019.
• ρ: Relaxed Hierarchical ORAM, Chandrasekhar Nagarajan, Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-24), Providence, April 2019. Lightning talk video
• The POP Detector: A Lightweight Online Program Phase Detection Framework , K. Taht, J. Greensky, R. Balasubramonian, International Symposium on Performance Analysis of Systems and Software (ISPASS), Madison, March 2019.
• ReTagger: An Efficient Controller for DRAM Cache Architectures , Mahdi Nazm Bojnordi and Farhan Nasrullah, 56'th Design Automation Conference (DAC), Las Vegas, Nevada, June 2019.
• STFL: Energy-Efficient Cache Interface using Slow Transition Fast Level Signaling , Payman Behnam and Mahdi Nazm Bojnordi, 56'th Design Automation Conference (DAC), Las Vegas, Nevada, June 2019.

2018

• Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration, Anirban Nag, Rajeev Balasubramonian, Vivek Srikumar, Ross Walker, Ali Shafiee, John Paul Strachan, Naveen Muralimanohar, IEEE Micro Special Issue on Memristor-Based Computing, September/October 2018.
• VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures, Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian, 23rd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-23), Williamsburg, March 2018.
• Secure DIMM: Moving ORAM Primitives Closer to Memory Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, 24th Annual IEEE International Conference on High Performance Computer Architecture (HPCA-24), Vienna, February 2018.
• Accelerating k-Medians Clustering Using a Novel 4T-4R RRAM Cell , Y. Rupesh, P. Behnam, G.Pandla, M. Miryala, and M. Bojnord, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2018.
• R-Cache: A Highly Set-Associative In-Package Cache using Memristive Arrays , P. Behnam, A. Chowdhury, and M. Bojnordi, 36th IEEE International Conference on Computer Design (ICCD), Orlando, Florida, Octobor 2018.
• X-Cache: A Highly Set-Associative In-Package Cache using Memristive Arrays , P. Behnam, A. Chowdhury, N. Rauniyar, N. Sedaghati, and M. Bojnordi, 56'th Design Automation Conference, Work-in-Progress Session(DAC-WIP), San francisco, California, June 2018.
• MB-CNN: Memristive Binary Convolutional Neural Networks for Embedded Mobile Devices, , Arjun Pal Chowdhury, Pranav Kulkarni, and Mahdi Nazm Bojnordi, Journal of Low Power Electronics and Applications (JLPEA): Special Issue on "Energy-Aware Neuromorphic Hardware", 2018.

2017

• CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas ACM Transactions on Architecture and Code Optimization (TACO-14), Manchester, January 2018.
• Adaptive Time-based Encoding for Energy-Efficient Large Cache Architectures Payman Behnam, Naser Sedaghati, Mahdi Nazm Bojnordi, 5th Annual ACM International Workshop on Energy Efficient Supercomputing (E2SC-5), Colorado, November 2017.
• INXS: Bridging the Throughput and Energy Gap for Spiking Neural Networks Surya Narayanan, Ali Shafiee, Rajeev Balasubramonian, 30th Annual IEEE International Joint Conference on Neural Networks (IJCNN-30), Anchorage, May 2017.

2016

• Enabling Technologies for Memory Compression: Metadata, Mapping, and Prediction Arjun Deb, Ali Shafiee, Rajeev Balasubramonian, Paolo Faraboschi, Naveen Muralimanohar, Robert Schreiber, 34th Annual IEEE International Conference on Computer Design (ICCD-34), Phoenix, October 2016.
• Understanding and Alleviating Intra-Die and Intra-DIMM Parameter Variation in the Memory System Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian, 34th Annual IEEE International Conference on Computer Design (ICCD-34), Phoenix, October 2016.
• ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar, 43rd Annual IEEE/ACM International Symposium on Computer Architecture (ISCA-43), Seoul, June 2016. Top Picks Honorable Mention
• Making the Case for Feature-Rich Memory Systems: The March Toward Specialized Systems, Rajeev Balasubramonian, IEEE Solid-State Circuits Magazine, Vol 8(2), June 2016.
• Addressing Service Interruptions in Memory with Thread-to-Rank Assignment , Manjunath Shevgoor, Rajeev Balasubramonian, Niladrish Chatterjee, Jung-Sik Kim, International Symposium on Performance Analysis of Systems and Software (ISPASS) , Uppsala, Sweden, April 2016. Best Paper Award

2015

• Efficiently Prefetching Complex Address Patterns Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Seth Pugsley, Chris Wilkerson and Zeshan Chishti, 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-48), Hawaii, December 2015.
• Avoiding Information Leakage in the Memory Controller with Fixed Service Policies Ali Shafiee, Akhila Gundu, Manjunath Shevgoor, Rajeev Balasubramonian and Mohit Tiwari, 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-48), Hawaii, December 2015.
• Improving Memristor Memory with Sneak Current Sharing Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian and Jeon Yoocharn, 33rd IEEE International Conference on Computer Design (ICCD), New York, October 2015.
• Fixed-Function Hardware Sorting Accelerators for Near Data MapReduce Execution Seth H. Pugsley, Arjun Deb, Rajeev Balasubramonian and Feifei Li, 33rd IEEE International Conference on Computer Design (ICCD), New York, October 2015.
• Overcoming the Challenges of Cross-Point Resistive Memory Architectures
  Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie. 21st IEEE International Symposium On High Performance Computer Architecture (HPCA-2015), Bay Area, Feb 2015.
• Efficiently Prefetching Complex Address Patterns Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian and Zeshan Chishti, The 2nd Data Prefetching Championship (DPC2) (held in conjunction with ISCA-42), Portland, June 2015.
• Designing a Fast and Reliable Main Memory with Memristor Technology (ppt) Manjunath Shevgoor, Naveen Muralimanohar and Rajeev Balasubramonian, 6th Non-Volatile Memories Workshop (NVMW), San Diego, March 2015.
• Designing a High-Performance Main Memory by Overcoming the Challenges of Crossbar Resistive Memory Architectures, Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie, 6th Non-Volatile Memories Workshop (NVMW), San Diego, March 2015.

2014

• Memory Considerations for Low Energy Ray Tracing
  Daniel Kopta, Konstantin Shkurko, Josef Spjut, Erik Brunvand, Al Davis. Computer Graphics Forum, 2014 [HWRT pub. page]
• Managing DRAM Latency Divergence in Irregular GPGPU Applications
  Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, and Rajeev Balasubramonian. 2014 IEEE/ACM International Conference for High Performance Computing, Networking, Storage, and Analysis (SC-2014) New Orleans, Nov 2014.
• Why Graphics Programmers Need to Know About DRAM
  Erik Brunvand, Daniel Kopta, Niladrish Chatterjee. ACM SIGGRAPH course, August 2014 [HWRT pub. page]
• Comparing Implementations of Near Data Computing with In-Memory MapReduce Workloads
  Seth Pugsley, Jeffrey Jestes, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li, IEEE Micro Special Issue on Big Data , July/August 2014.
• Near-Data Processing: Insight from a Workshop at MICRO-46
  Rajeev Balasubramonian, Jichuan Chang, Troy Manning, Jaime Moreno, Richard Murphy, Ravi Nair, Steve Swanson, IEEE Micro Special Issue on Big Data , July/August 2014.
• Memory Bandwidth Reservation in the Cloud to Avoid Information Leakage in the Memory Controller
  Akhila Gundu, Gita Sreekumar, Ali Shafiee, Seth Pugsley, Hardik Jain, Rajeev Balasubramonian, Mohit Tiwari, 3rd Workshop on Hardware and Architectural Support for Security and Privacy (HASP), held in conjunction with ISCA-41, Minneapolis, June 2014.
• NDC: Analyzing the Impact of 3D-Stacked Memory+Logic Devices on MapReduce Workloads
  Seth Pugsley, Jeffrey Jestes, Huihui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis and Feifei Li, 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS-2014) Monterey, March 2014.
• Exploring a Brink-of-Failure Memory Controller to Design an Approximate Memory System,
  Meysam Taassori, Niladrish Chatterjee, Ali Shafiee, Rajeev Balasubramonian, 1st Workshop on Approximate Computing Across the System Stack (WACAS), held in conjunction with ASPLOS-19, Salt Lake City, March 2014.
• MemZip: Exploring Unconventional Benefits from Memory Compression
  Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian, Al Davis, 20th IEEE International Symposium On High Performance Computer Architecture (HPCA-2014) , Orlando, Feb 2014.
• Sandbox Prefetching: Safe Run-Time Evaluation of Aggressive Prefetchers
  Seth H Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L Scott3, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, and Rajeev Balasubramonian, 20th IEEE International Symposium On High Performance Computer Architecture (HPCA-2014) Orlando, Feb 2014. Top Picks Honorable Mention

2013

• Quantifying the Role of the Power Delivery Network and Architectural Policies in 3D-Stacked Memory Devices
  Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha N.Udipi, 46th International Symposium on Microarchitecture (MICRO-46), Davis, Dec 2013.
• An Energy and Bandwidth Efficient Ray Tracing Architecture
  Daniel Kopta, Konstantin Shkurko, Josef Spjut, Erik Brunvand, Al Davis. High Performance Graphics (HPG) , Anaheim, July 2013. [HWRT pub. page]
• A Novel System Architecture for Web-Scale Applications Using Lightweight CPUs and Virtualized I/O
  Kshitij Sudan, Saisantosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian, 19th International Symposium on High Performance Computer Architecture (industrial track) (HPCA-19), Shenzhen, China, 2013.
• Understanding the Role of the Power Delivery Network in 3D-Stacked Memory Devices
  Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, AniruddhaN.Udipi, 5th Workshop on Energy Efficient Design (WEED 2013, held in conjunction with ISCA-40), Tel Aviv, June 2013.

2012

• Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access, Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi Iyer, 45th International Symposium on Microarchitecture (MICRO-45) , Vancouver, December 2012.
• Optimizing Datacenter Power with Memory System Levers for Guaranteed Quality-of-Service , Kshitij Sudan, Sadagopan Srinivasan, Rajeev Balasubramonian, Ravi Iyer, 21st International Symposium on Parallel Architectures and Compilation Techniques (PACT-21) , Minneapolis, September 2012.
• LOT-ECC: LOcalized and Tiered Reliability Mechanisms for Commodity Memory Systems , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 39th International Symposium on Computer Architecture (ISCA-39) , Portland, June 2012.
• Fast, Effective BVH Updates for Animated Scenes, Daniel Kopta, Thiago Ize, Josef Spjut, Erik Brunvand, Al Davis and Andrew Kensler, ACM SIGGRAPH Symposium on Interactive 3D Graphics and Games (I3D 2012), Irvine, March 2012. [HWRT pub. page]
• Efficient Scrub Mechanisms for Error-Prone Emerging Memories , Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan, 18th International Symposium on High-Performance Computer Architecture (HPCA-18) , New Orleans, February 2012.
• Staged Reads: Mitigating the Impact of DRAM Writes on DRAM Reads , Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 18th International Symposium on High-Performance Computer Architecture (HPCA-18) , New Orleans, February 2012.
• A Mobile Accelerator Architecture for Ray Tracing, Josef Spjut, Daniel Kopta, Erik Brunvand and Al Davis, 3rd Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW-3), New Orleans, February 2012. [HWRT pub. page]
• Managing Data Placement in Memory Systems with Multiple Memory Controllers , Manu Awasthi,Dave Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis, International Journal of Parallel Programming (IJPP) , Vol 40(1), February 2012.
• USIMM: the Utah SImulated Memory Module , Niladrish Chatterjee, Rajeev Balasubramonian, Manjunath Shevgoor, Seth H. Pugsley, Aniruddha N. Udipi, Ali Shafiee, Kshitij Sudan, Manu Awasthi, Zeshan Chishti, Technical Report UUCS-12-002, February 2012.

2011

• Combining Memory and a Controller with Photonics through 3D-Stacking to Enable Scalable and Energy-Efficient Systems , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 38th International Symposium on Computer Architecture (ISCA-38), San Jose, June 2011. CRA Research Highlight .
• CHOP: Integrating DRAM Caches for CMP Server Platforms , Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian, IEEE Micro's Special issue on Top Picks from 2010 Computer Architecture Conferences , January/February 2011.
• Prediction Based DRAM Row-Buffer Management in the Many-Core Era , Manu Awasthi, David Nellans, Rajeev Balasubramonian, Al Davis, Proceedings of PACT-20 (poster session, second prize) Galveston Island, October 2011.
• Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures , Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall, Rajeev Balasubramonian, Proceedings of PACT-20 (poster session) Galveston Island, October 2011.
• Refining the Utility Metric for Utility-Based Cache Partitioning , Xing Lin, Rajeev Balasubramonian, 9th Workshop on Duplicating, Deconstructing, and Debunking (WDDD), held in conjunction with ISCA-38, San Jose, June 2011.
• Handling PCM Resistance Drift with Device, Circuit, Architecture, and System Solutions , Manu Awasthi, Manju Shevgoor, Kshitij Sudan, Rajeev Balasubramonian, Bipin Rajendran, Viji Srinivasan, 2nd Non-Volatile Memories Workshop (NVMW), San Diego, March 2011.

2010

• Efficient MIMD Architectures for High-Performance Ray Tracing, Daniel Kopta, Josef Spjut, Alan Davis and Erik Brunvand, IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, October 2010. [HWRT pub. page]
• Handling the Problems and Opportunities Posed by Multiple On-Chip Memory Controllers, Manu Awasthi, David Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis, 19th International Conference on Parallel Architectures and Compilation Techniques (PACT-19) , Vienna, September 2010 (Best paper award).
• SWEL: Hardware Cache Coherence Protocols to Map Shared Data onto Shared Caches, Seth H. Pugsley, Josef Spjut, David Nellans, Rajeev Balasubramonian, 19th International Conference on Parallel Architectures and Compilation Techniques (PACT-19) , Vienna, September 2010.
• Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores , Aniruddha Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norm Jouppi, 37th International Symposium on Computer Architecture (ISCA-37) , St. Malo, France, June 2010.
• Micro-Pages: Increasing DRAM Efficiency with Locality-Aware Data Placement , Kshitij Sudan, Niladrish Chatterjee, David Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis, 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV) , Pittsburgh, March 2010.
• Towards Scalable, Energy-Efficient, Bus-Based On-Chip Networks , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
• CHOP: Adaptive Filter-based DRAM Caching for CMP Server Platforms , Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravi Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian, 16th International Symposium on High-Performance Computer Architecture (HPCA-16) , Bangalore, January 2010.
• Improving Server Performance on Multi-Cores via Selective Off-loading of OS Functionality , David Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian, 6th Workshop on Interaction between Operating Systems and Computer Architecture (WIOSCA), held in conjunction with ISCA-37, St. Malo, France, June 2010.
• Rethinking DRAM Design for Low-Power Datacenters, Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC)(poster session, best poster presentation award), India, December 2009.

2009

• TRaX: A Multicore Architecture for Real-Time Ray Tracing, Josef B. Spjut, Andrew E. Kensler, Daniel Kopta and Erik L. Brunvand, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Dec 2009. [HWRT pub. page]
• Non-Uniform Power Access in Large Caches with Low-Swing Wires , Aniruddha Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, 16th International Conference on High Performance Computing (HiPC) , Kochi, December 2009 (Best paper award).
• Hardware-accelerated gradient noise for graphics, Josef B. Spjut, Andrew E. Kensler and Erik L. Brunvand, Proceedings of the 19th ACM Great Lakes Symposium on VLSI (GLSVLSI'09) Boston, May 10 - 12, 2009. [HWRT pub. page]
• Optimizing a Multi-Core Processor for Message-Passing Workloads , Niladrish Chatterjee, Seth H. Pugsley, Josef Spjut, Rajeev Balasubramonian, 5th Workshop on Unique Chips and Systems (UCAS-5), held in conjunction with ISPASS, Boston, April 2009.
• OS Execution on Multi-Cores: Is Out-Sourcing Worthwhile?, David Nellans, Rajeev Balasubramonian, and Erik Brunvand, Position paper in ACM Operating System Review, Special Issue on Interaction among OS, Compilers, and Multicore Processors , April 2009.
• Dynamic Hardware-Assisted Software-Controlled Page Placement to Manage Capacity Allocation and Sharing within Large Caches , Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John Carter, 15th International Symposium on High-Performance Computer Architecture (HPCA-15), Raleigh, February 2009.
• Optimizing Communication and Capacity in a 3D Stacked Reconfigurable Cache Hierarchy , Niti Madan, Li Zhao (Intel), Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni ,Donald Newell, 15th International Symposium on High-Performance Computer Architecture (HPCA-15) , Raleigh, February 2009.
• Interference Aware Cache Designs for Operating System Execution , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, Technical Report UUCS-09-002, February 2009.

2008

• Scalable and Reliable Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, 17th International Conference on Parallel Architectures and Compilation Techniques (PACT-17) , Toronto, October 2008.
• TRaX: A Multi-Threaded Architecture for Real-Time Ray Tracing, Josef B. Spjut, Solomon Boulos, Daniel Kopta, Erik L. Brunvand and Spencer Kellis, Symposium on Application Specific Processors (SASP), Anaheim, 8-9 June 2008 (Best paper award).[HWRT pub. page]
• Architecting Efficient Interconnects for Large Caches with CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi (HP Labs), IEEE Micro's Special issue on Top Picks from 2007 Computer Architecture Conferences, Jan/Feb 2008.
• Scalable, Reliable, Power-Efficient Communication for Hardware Transactional Memory , Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian, Technical Report UUCS-08-001, January 2008.

2007

• Optimizing NUCA Organizations and Wiring Alternatives for Large Caches With CACTI 6.0 , Naveen Muralimanohar, Rajeev Balasubramonian, Norm Jouppi, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Leveraging 3D Technology for Improved Reliability, Niti Madan, Rajeev Balasubramonian, 40th International Symposium on Microarchitecture (MICRO-40) , Chicago, December 2007.
• Commit Algorithms for Scalable Hardware Transactional Memory , Seth H. Pugsley, Rajeev Balasubramonian, Technical Report UUCS-07-016, August 2007.

2006

• Leveraging Wire Properties at the Microarchitecture Level , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, and John Carter, IEEE Micro , Vol. 26, No. 6, November/December 2006.
• Exploring the Design Space for 3D Clustered Architectures , Manu Awasthi, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
• The Effect of Interconnect Design on the Performance of Large L2 Caches , Naveen Muralimanohar, Rajeev Balasubramonian, 3rd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, October 2006.
• Interconnect-Aware Coherence Protocols for Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 33rd International Symposium on Computer Architecture (ISCA-33) , Boston, June 2006.
• Power Efficient Resource Scaling in Partitioned Architectures through Dynamic Heterogeneity , Naveen Muralimanohar, Karthik Ramani, and Rajeev Balasubramonian, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) , Austin, March 2006.
• Exploiting Eager Register Release in a Redundantly Multi-Threaded Processor , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on Architectural Reliability (WAR-2), held in conjunction with MICRO-39, Orlando, December 2006.
• Leveraging Bloom Filters for Smart Search Within NUCA Caches , Robert Ricci, Steve Barrus, Dan Gebhardt, Rajeev Balasubramonian, 7th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-33 , Boston, June 2006.
• Re-Visiting the Performance Impact of Microarchitectural Floorplanning , Anupam Chakravorty, Abhishek Ranjan, Rajeev Balasubramonian, 3rd Workshop on Temperature Aware Computer Systems (TACS), held in conjunction with ISCA-33 , Boston, June 2006.
• A First-Order Analysis of Power Overheads of Redundant Multi-Threading , Niti Madan, Rajeev Balasubramonian, 2nd Workshop on the System Effects of Logic Soft Errors (SELSE-2) , Urbana, April 2006.

2005

• A Case for Increased Operating System Support in Chip Multi-Processors , David Nellans, Rajeev Balasubramonian, and Erik Brunvand, 2nd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers (P=ac2) , Yorktown Heights, September 2005.
• Microarchitectural Wire Management for Performance and Power in Partitioned Architectures , Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, and Venkatanand Venkatachalapathy, 11th International Symposium on High-Performance Computer Architecture (HPCA-11) , San Francisco, February 2005.
• Wire Management for Coherence Traffic in Chip Multiprocessors , Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, and John Carter, 6th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-32 , Madison, June 2005.
• Power-Efficient Approaches to Reliability , Niti Madan, Rajeev Balasubramonian, Technical Report UUCS-05-010, December 2005.

2004

• Cluster Prefetch: Tolerating On-Chip Wire Delays in Clustered Microarchitectures , Rajeev Balasubramonian, 18th International Conference on Supercomputing (ICS-18) , Saint-Malo, June 2004.
• Microarchitectural Techniques to Reduce Interconnect Power in Clustered Processors , Karthik Ramani, Naveen Muralimanohar, and Rajeev Balasubramonian, 5th Workshop on Complexity-Effective Design (WCED), held in conjunction with ISCA-31 , Munich, June 2004.